FIG. 1 illustrates a cross-section of a flash memory cell in a nonvolatile semiconductor memory device. Referring to FIG. 1, the flash memory cell includes a source 3 and a drain 4, which are formed on a P-type semiconductor substrate 2 using N+ impurities such that a channel region is disposed between the source 3 and the drain 4; a floating gate 6, which is disposed above the channel region such that a first insulating layer 7 (e.g., a thin tunnel oxide layer) having a thickness of 100 Å or less is disposed between the channel region and the floating gate 6; and a control gate 8, which is insulated from the floating gate 6 by a second insulating layer 7 (e.g., an ONO layer) disposed between the control gate 8 and the floating gate 6. The source 3, the drain 4, the control gate 8, and the semiconductor substrate 2 are connected with power supply terminals Vs, Vd, Vg, and Vb, respectively, in order to apply voltages necessary for programming (write), erase, and read operations of a semiconductor memory device (see FIG. 2).
In the programming (write) operation of the conventional flash memory, hot electron injection occurs from the channel region adjacent to the drain 4 into the floating gate 6, thereby programming the flash memory cell. The electron injection is carried out by grounding the source 3 and the semiconductor substrate 2, applying a high voltage of 10 V to a control gate electrode Vg, and applying a voltage of 5V to 6 V, which is appropriate for generating hot electrons, to the drain 4. When the flash memory cell is programmed through the voltage application, significant negative charges are accumulated at the floating gate 6 so as to serve to increase a threshold voltage of the programmed flash memory cell detectible during the next read operation.
However, in the conventional flash memory, when a cell adjacent to a programmed cell is programmed, the threshold voltage of the previously programmed (adjacent) cell changes due to the influence of charges accumulated at the currently programmed cell, i.e., due to capacitive floating gate coupling. In particular, when a flash memory cell can have multiple states, a margin between the states is narrow, and therefore, a programming method for reducing the floating gate coupling is needed.
FIG. 2 illustrates a cell structure in a nonvolatile NOR semiconductor memory. Referring to FIG. 2, the threshold voltage of a first cell T is influenced by prior programming of adjacent cells C1, C2, C3, C4, B1, B2, W1, and W2. The influence of the adjacent cells B1, B2, and W1 may be large while the influence of the adjacent cells C3, C4, and W2, which have a metal contact MC interposed between the cell T and each of the cells C3, C4, and W2, may be slight.
The threshold voltage of the cell T is affected when any of the adjacent cells C1, C2, C3, C4, B1, B2, W1, or W2 is programmed. The amount of change in the threshold voltage of the cell T is approximately proportional to the amount of charges accumulated in each of the adjacent cells C1, C2, C3, C4, B1, B2, W1, or W2 in a programmed state. For example, the threshold voltage of cell T is affected most when any of the adjacent cells C1, C2, C3, C4, B1, B2, W1, or W2 is programmed from an erased state to a highest state (e.g., a “00” state). In order to minimize this influence, each cell is programmed to a voltage lower than the target threshold voltage of each state under the influence of floating gate coupling until the cell is programmed to a final target threshold voltage, thereby reducing the influence of the floating gate coupling.
FIG. 3 illustrates threshold voltage distributions to explain a conventional programming method of a conventional nonvolatile semiconductor memory device. FIG. 3 shows target threshold voltage distributions (i.e., ranges defined by solid lines) in a memory cell having four states (e.g., a “00” state, a “01” state, a “10” state, and a “11” state).
According to the conventional programming method, in step S1 cells to be programmed are programmed to a voltage a predetermined level lower than a target voltage of a third state (e.g., the “10” state). Thereafter, in step S2, among the programmed cells, cells to be programmed to a second state (e.g., the “01” state) are programmed to a voltage a predetermined level lower than a target voltage of the second state. In step S3, among the cells programmed in step S2, cells to be programmed to a first state (e.g., the “00” state) are programmed to a voltage a predetermined level lower than a target voltage of the first state.
Thereafter, in step S4, cells to be programmed to the third state (e.g., the “10” state) are programmed from the state programmed in step S1 to the target threshold voltage of the third state. In step S5, the cells to be programmed to the second state (e.g., the “01” state) are programmed from the state programmed in step S2 to the target threshold voltage of the second state. In step S6, the cells to be programmed to the first state (e.g., the “00” state) are programmed from the state programmed in step S3 to the target threshold voltage of the first state.
As described above, a cell is programmed to a voltage lower than the target threshold voltage of each state under the influence of floating gate coupling so that the distribution of the threshold voltage changing due to the floating gate coupling corresponds with the distribution of the target threshold voltage, thereby mitigating the influence of the floating gate coupling as a whole. However, as illustrated in FIG. 3, the number of programming operations increases, which increases entire programming time, and thus reduces the effective speed of the memory device.
Therefore, a programming method and memory device for reducing the number of programming operations and for reducing the floating gate coupling effect are desired.